`include "define.v"
module ppregs_F
    (
	input  clk,
	input  rst_n,
	input  F_stall,
	input  [31:0]predPC_i,
	output reg [31:0]predPC_o
    );

    always @ (posedge clk or negedge rst_n)
    begin
	if(~rst_n)
	    begin
		predPC_o<=0;
	    end
	else
	    begin
		predPC_o<=F_stall?predPC_o:predPC_i;
	    end
    end


endmodule
